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    "name": "clock input for the chip",
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      "timestamp": "2026-10-13T11:07:53.826+00:00",
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      "content": "Hi, i still have a doubt about the clock input. so far, what i understand, that we should provide the clock from outside directly with frequency input what we want, is that right?\n\nI mean, we don't use PLL to get clock from crystal, or something like that.\n\nSo, how normally people feed the clock for their tapeout chip? and what is reasonable frequency to achieve? \n\nThank you.",
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      "content": "Hi! You tell LibreLane what clock period should be achieved using the `CLOCK_PERIOD` variable.\nIf that clock period cannot be achieved for your design, the flow will error out.\n\nOnce you have your chip, you can supply an external clock signal up to that frequency. Of course, you can always supply a lower clock frequency (if you don't use dynamic flip-flops, which is the case for the default SCL).",
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      "content": "@Leo Moser (mole99) - How does that work with hold time requirements?",
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      "content": "Hold time is independent of the clock period/frequency. Clock tree synthesis and the resizer ensure that your design is free from hold violations over all specified corners, and OpenSTA will verify this after parasitic extraction.",
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